Encryptor and decryptor system for the RSA cryptographic system based on the residual number representation RNS (Residue Number System) and the CRT theorem, performing counter-synchronized signal processing representing partial data of modular exponentiation operations occurring in two parallel data streams, alternating switching of these signals by means of the modular exponentiation (UOPM) system between two parallel operating modular exponentiation systems SPM-1 and SPM-2, synchronously with the CLK clock signal at such a high frequency that, according to the current state of the art, selective interference of signals representing only one of two data streams, which effectively eliminates the possibility of cryptanalysis based on the injection of errors into the semiconductor system.
More information on this patent: https://ewyszukiwarka.pue.uprp.gov.pl/search/pwp-details/P.425306